The present invention is related to the transmission of data between a host computer and users in a data processing system, and is more particularly related to positioned or time slot protocol transmissions in a data processing system.
Various protocol arrangements have been established for the communication of data between a host computer and a community of users in a data processing system network. One such arrangement is a time positioned or time slot protocol in which each user is assigned a time slot in a frame of data in which to send or receive data in the frame.
U.S. Pat. No. 3,784,752, to Peron, issued Jan. 8, 1974 for "Time Division Data Transmission System", discloses a telephonic data transmission system for transmission of data through a chain of cascaded, asynchronous, time-division switching networks in which a number of time slots employed for the transmission of data is variable, and is subject to the flow of information to be transmitted.
U.S. Pat. No. 3,787,631, to Lewis, issued Jan. 22, 1974 for "Time Slot Number Compensating Arrangement", discloses a telephonic data transmission system having a plurality of port circuits, with each port circuit having an individual shift register for defining the time interval during which a connection may take place. A circulating bit is used to assign a port circuit to a specific-time slot.
U.S. Pat. No. 4,161,629, to Kits van Heyningen, issued July 17, 1979 for "Communication System With Selectable Data Storage", discloses a communication system wherein a predetermined number of time slots is provided for each of sequentially occurring scans of the sending stations, with each slot providing for the transmission of a preset number of data samples. Switching circuitry and registers are employed for enabling the available time slots to be assigned to stations in accordance with the average data rate of a message.
U.S. Pat. No. 4,229,792, to Jensen et al., issued Oct. 21, 1980 for "Bus Allocation Synchronization System", discloses a bus allocation system for controlling a time division multiplexed digital data bus used by a plurality of signal sources in which no single signal source controls the bus. Each signal source has an address counter which operates in conjunction with an allocation vector. Each address counter is synchronized during or following the receipt of a message to prevent interference by more than one device using the bus at a given time.
U.S. Pat. No. 4,236,203, to Curley et al., issued Nov. 25, 1980 for "System Providing Multiple Fetch Bus Cycle Operation", discloses a data communications system wherein information may be transferred by the requesting unit having the highest priority during an asynchronously generated bus transfer cycle. Logic is provided for enabling a master unit to request information from a slave unit during a first bus transfer cycle, wherein the information from the slave unit is transferred from the slave unit during a series of later slave generated bus cycles.
U.S. Pat. No. 4,241,444, to Kister, issued Dec. 23, 1980 for "Arrangement for Time-Division Multiplex PWM Data Transmission", discloses a time-division multiplex data transmission system in which each subscriber on the system has a programmable counter which can be reset synchronously with the programmable counters of the other subscribers for determining the end of a time frame.
U.S. Pat. No. 4,340,961, to Copel et al., issued July 20, 1982 for "Distributed Multi-Port Communications System", discloses a distributed multi-port communications system wherein terminals may communicate with one another during sequential poll cycles to fulfill low data rate requirements, or during a burst cycle to fulfill high data rate requirements. Each poll cycle includes a number of time slots with at least one time slot assigned to each terminal during which it can transmit data to any other terminal or request for a burst cycle.
U.S. Pat. No. 4,535,446, to Mountain, issued Aug. 13, 1985 for "Digital Transmission Systems", discloses an aligner which can operate as a time switch to avoid clashes between reading and writing to a store by allowing slippage of one frame.